ALINT design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage. Smart design rule checking (linting) points out coding style, functional, and structural problems that are extremely difficult to debug in simulators and prevents those issues from spreading into the downstream stages of design flow. The tool features highly customizable and intuitive framework that seamlessly integrates into existing environments and helps to automate any existing design guidelines. The framework delivers configurable sets of rules, efficient Phase-Based Linting (PBL) methodology, and feature rich result-analysis tools.
制造商 Aldec 中国 Aldec 中国
北京
主要功能 芯片RTL编码
软件类型 商业软件
部署方式 本地部署

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Top Features：

  • Fast design analysis of complex ASIC/FPGA/SOC designs
  • Phase-Based Linting (PBL) Methodology
  • IEEE VHDL, Verilog and mixed-language designs
  • STARC VHDL or Verilog rule plug-ins
  • DO-254/ED-80 VHDL or Verilog rule plug-ins
  • RMM rule plug-in (both Verilog and VHDL)
  • Custom rule creation (C++ API)
  • Integrated result analysis and debugging environment
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