Aldec

公司介绍

Aldec公司是一家业界领先的电子设计自动化（EDA）公司，在复杂的FPGA中提供创新的设计制作，仿真和验证，协助ASIC的开发解决方案，SOC与嵌入式系统设计。在社区超过35000个活跃的用户，50 +全球合作伙伴，全球办事处和全球销售分销网络超过43个国家，作为一个成熟的领导者，该公司已建立了自己的验证设计界。Aldec公司提供政府，军事，航空航天，电信高质量的EDA解决方案，关键应用于汽车和安全。大公司包括IBM、GE、高通、Rohde和Schwarz，博世，德克萨斯仪器，应用微、休利特帕卡德、东芝、英特尔、NEC、三菱、LG、日立、美国宇航局、英维思、西屋公司、雷神、松下、洛克希德马丁、三星，以及中小企业利用Aldec公司EDA验证套件提高产品性能，降低设计开发周期，降低成本。

更新时间：2025-06-05

软件产品

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Aldec OEM 模拟器将业界领先的 VHDL 和 Verilog 仿真功能引入 Altium Designer 统一环境，完美地补充了 Altium Designer 强大的 FPGA 设计功能。

电子电路仿真

2.4w浏览

ALINT design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage. Smart design rule checking (linting) points out coding style, functional, and structural problems that are extremely difficult to debug in simulators and prevents those issues from spreading into the downstream stages of design flow. The tool features highly customizable and intuitive framework that seamlessly integrates into existing environments and helps to automate an...

芯片RTL编码

2.2w浏览

Aldec and Microsemi have joined together, offering a new, innovative, reprogrammable prototyping solution for Microsemi RTAX-S/SL, RTAX-DSP and RTSX-SU space-fight system designs. Unlike the traditional OTP (One Time Programmable) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses flash-based, Microsemi ProASIC3E FPGA technology, for design prototype re-programmability.

嵌入式软件开发平台

2.3w浏览

HES-7 provides SoC/ASIC hardware verification and software validation teams with a scalable and high quality FPGA-based ASIC prototyping solution backed with an industry leading 1-year limited warranty. Each HES7XV4000BP board (2x Xilinx Virtex-7 2000T) has up to 24M ASIC gates of capacity, while latest HES7XV12000BP board (6x Xilinx Virtex-7 2000T) has up to 72M ASIC gates, not including the DSP and memory resources.

电子电路仿真

1.8w浏览

DO-254/CTS is a fully customized hardware and software platform that augments target board testing to increase verification coverage by test and satisfy the verification objectives of DO-254/ED-80. The target design runs at-speed in the target device mounted on the custom daughter board. The simulation testbench is used as test vectors to enable requirements-based testing with 100% FPGA pin-level controllability and visibility necessary to implement normal range and abnormal range tests. The FPG...

可靠性分析/安全性分析

2.3w浏览

HES-DVM is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accurate and speed-effective SoC emulation models reducing test time and a risk of silicon re-spins.

芯片设计物理验证

2.5w浏览

CyberWorkBench 允许设计人员在算法层面实现硬件，从而提高芯片的设计效率、低功耗和高性能。这款适用于 ASIC 和 FPGA（Xilinx/Altera）的“全 C”高级综合和验证工具集，可显著缩短开发时间和成本。设计人员可以使用 SystemC 和 ANSI-C 在更高的抽象级别描述硬件，并使用 CyberWorkBench 为其 ASIC 和 FPGA（Xilinx/Altera）芯片生成高度优化的 RTL 代码。与手动 RTL 设计方法相比，自动流水线、功耗优化和强大的并行提取功能使设计人员能够生成更小、更低功耗的设计。

芯片RTL编码

2.1w浏览

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

芯片电路仿真

2.8w浏览

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