“全 C 语言”综合
CyberWorkBench 中的行为综合器可以综合任何类型的应用，包括控制主导电路和数据路径。这款一流的高级综合器具有自动流水线、功耗优化和强大的并行提取功能，可通过最大程度地共享资源来减少芯片面积和功耗。拥有 IP/RTL 旧模块的设计人员可以使用顶层结构描述生成器，并轻松连接到基于 C 语言的模块。为了提高设计效率，CyberWorkBench 还包含大量行为 IP，可根据不同的实现技术或系统需求进行重新定位。
“全 C 语言”验证
CyberWorkBench 提供强大的静态和动态验证工具，使大型设计的调试更加轻松。使用 C 语言属性检查器对高级源代码进行形式化验证，使设计人员能够直接在 C 语言源代码中描述断言和属性。内置的自动化测试平台生成器允许在 SystemC 和 RTL 仿真中重复使用未计时的 C 语言激励，从而缩短验证时间。
主要优势
支持控制主导电路和数据路径模块
为 Altera 和 Xilinx FPGA 提供专业的技术支持
一流的高级综合器，具有自动流水线、功耗优化和强大的并行提取功能
强大的综合电路图形分析功能
使用断言和属性进行基于 C 语言的形式化验证
自动顶层结构描述生成器，用于连接基于 C 语言的模块和传统 RTL 模块
强大的 SystemC 源代码调试器
传统/IP RTL 代码到 SystemC 的转换器，可更轻松地迁移到基于 C 语言的设计流程
“All-in-C” Synthesis
Behavioral synthesizer in CyberWorkBench can synthesize any type of application including control dominated circuits and datapath. This best-in-class high-level synthesizer features automatic pipelining, power optimization and powerful parallelism extraction to reduce chip area and power through maximum resource sharing. Designers with IP/RTL legacy modules can use top level structural description generator and can easily connect to C-based modules. To improve the design productivity CyberWorkBench also includes numerous behavioral IPs that can be retargeted to different implementation technologies or system requirements.
“All-in-C” Verification
CyberWorkBench provides powerful static and dynamic verification tools to make debugging of larger designs much easier. Formal verification of the high level source code using C level property checker enables designers to describe assertions and properties directly in C source code. Built-in automated testbench generator cuts verification time by allowing re-usage of untimed C stimulus in SystemC and RTL simulation.
Top Benefits
- Support for both control dominated circuits and datapath module
- Dedicated technology support for Altera & Xilinx FPGAs
- Best-in-class High-Level Synthesizer that features automatic pipelining, power optimization, powerful parallelism extraction
- Powerful graphical analysis capabilities for synthesized circuits
- C-based Formal Verification using assertions and properties
- Automatic top level structural description generator to connect C-based modules and legacy RTL modules
- Powerful SystemC source code debugger
- Legacy/IP RTL code to SystemC converter for easier migration to C-based design flow
